1. Field of the Invention
The present invention relates to a power supply circuit of a synchronous rectification type that offers fast response to a variation in load.
2. Description of Related Art
Power supply circuits are used in power supplies for PCs (personal computers), power supplies for servers, power supplies for FPGAs (field-programmable gate arrays), power supplies for SOCs (systems-on-a-chip), power supplies for OA (office automation) appliances, etc. In a power supply circuit, through switching operation whereby transistors are turned ON and OFF in accordance with variations in load and in input, the output voltage as a supply voltage is stabilized. This helps reduce wasted electric power, leading to improved energy efficiency. One example of such efficient power supply circuits is switching regulators of a synchronous rectification type that employ a CMOS (complementary metal-oxide-semiconductor transistor) integrated circuit.
Patent Document 1 (Japanese Patent Application Publication No. 2004-88950) discloses a power supply circuit in which the output voltage is compared with a reference voltage, then an error signal is fed back to a PWM (pulse-width modulation) circuit, and then the pulse width of a PWM signal is controlled according to the error signal; thereby a CMOS inverter is controlled so as to keep the output voltage constant.
Patent Document 2 (Japanese Patent Application Publication No. 2004-56982) discloses a power supply circuit in which the output voltage of a CMOS inverter is monitored to detect if it has recovered from an undershoot and exceeded a reference potential, then a signal indicating the magnitude of the load current is fed back to a PWM circuit, and then the pulse width of PWM is controlled; thereby the output voltage is made to cope with variations in load.
Patent Document 3 (Japanese Patent Application Publication No. 2000-92824) discloses a power supply circuit in which the direction of the current passing through a smoothing circuit is detected, and a switch is forcibly turned OFF so as to reduce direct-current power loss when the load current is high.
FIG. 4 is a circuit diagram showing a power supply circuit, different from any of those disclosed in Patent Documents 1 to 3, that came to the knowledge of the present inventor. The power supply circuit shown in FIG. 4 is composed of a control circuit 10a, a first transistor M1a, a second transistor M2a, an inductor La, a capacitor Ca, a resistor Ra, a resistor Rb, a comparator CMPa, and an error amplifier ERRa. Between a source S and a drain D of the first transistor M1a, a parasitic diode D1a is formed. Between a source S and a drain D of the second transistor M2a, a parasitic diode D2a is formed.
The control circuit 10a outputs driving signals S1a and S2a to turn ON and OFF the first and second transistors M1a and M2a alternately. Thus, a rectangular-wave voltage is output to a node Na. The rectangular-wave voltage and the inductor La cause a triangular-wave current ILa to pass through the inductor La. The triangular-wave current ILa is smoothed by the capacitor Ca, and an output voltage Voa is produced at an output terminal OUT. Thus, when a load RL is connected to the output terminal OUT, an output current ba is output. The load RL is, for example, a CPU. The output voltage Voa at the output terminal OUT is divided by the resistors Ra and Rb, and thereby a feedback voltage Vfba is produced at a node Nc. The error amplifier ERRa compares the feedback voltage Vfba with a reference voltage Vrefa, and outputs a control signal Vera that reflects the result of the comparison. The control signal Vera is fed to the control circuit 10a. Based on the control signal Vera fed to it, the control circuit 10a controls the switching of the first and second transistors M1a and M2a so that the output current ba remains constant.
In the power supply circuit shown in FIG. 4, when the load RL connected to the output terminal OUT turns from a heavy load to a light or no load, the output current boa passing through the output terminal OUT decreases, and thus the output voltage Voa rises. This is called an overshoot. Poor response to a variation in load cause a large overshoot. With the power supply circuit shown in FIG. 4, when the load RL connected to the output turns from a heavy load to a light or no load and the feedback voltage Vfba exceeds the value of the reference voltage Vrefa, a detection signal Vcma output from the comparator CMPa turns from high level H to low level L. The reference voltage Vrefa is set at a level higher than the feedback voltage Vfba. In response to the detection signal Vcma at low level L, the control circuit 10a turns the driving signal S2 to low level L to forcibly turn OFF the second transistor M2a. This reduces the overshoot in the feedback voltage Vfba. For the purpose of turning OFF the second transistor M2a when the load RL turns from a heavy load to a light or no load, the polarity of the detection signal Vcma output from the comparator CMPa does not matter: it may be at low level L or at high level H.
FIG. 5 is a timing chart of the power supply circuit shown in FIG. 4. Now, with reference to FIGS. 4 and 5, the circuit operation of the power supply circuit will be described.
From time point T0 to time point T6, by the driving signals S1a and S2a, the first and second transistors M1a and M2a are kept turning ON and OFF alternately, with a result that a triangular-wave current passes through the inductor La. The triangular-wave current is smoothed by the capacitor Ca, so that a constant output current ba passes through the output terminal OUT.
From time point T6 to time point T7a, the load RL connected to the output terminal OUT turns from a heavy load to a light or no load. Thus, the output current Ioa passing through the output terminal OUT decreases. As a result, the output voltage Voa rises, and accordingly the feedback voltage Vfba rises. At this time, the feedback voltage Vfba is lower than the reference voltage Vrefa, and thus the second transistor M2a is kept ON.
At time point T8a, the level of the feedback voltage Vfba exceeds the level of the reference voltage Vrefa, and the comparator CMPa turns the detection signal Vcma from high level H to low level L. Based on the detection signal Vcma, the control circuit 10a turns the driving signal S2a from high level H to low level L. Thus, the second transistor M2a is forcibly turned OFF. As a result, the current path leading through the ground terminal GND back to the inductor La is cut off, and thus the current ILa passing through the inductor La decreases faster. That is, the current ILa passing through the inductor La decreases faster when the second transistor M2a is turned to OFF than when the second transistor M2a is kept ON. As a result, an overshoot in the feedback voltage Vfba is suppressed. When the second transistor M2a is ON, the current ILa takes a path ILa1 and the feedback voltage Vfba takes a path Vfba1; when the second transistor M2a is turned OFF, the current IL takes a path ILa2, and the feedback voltage Vfba takes a path Vfba2.
After time point T8a, when the feedback voltage Vfba becomes lower than a reference voltage Vrefb, the error amplifier ERRa turns the control signal Vera from low level L to high level H. Based on the control signal Vera, the control circuit 10a turns the driving signal S1a from low level L to high level H, and turns the driving signal S2a from high level H to low level L. Thus, the first transistor M1a is turned from OFF to ON, and the second transistor M2a is turned from ON to OFF. Thereafter, the first and second transistors M1a and M2a are so controlled as to keep turning ON and OFF complementarily. Here, “complementarily” is assumed to cover not only operation where the ON/OFF states of the first and second transistors M1a and M2a are completely reversed, but also operation where, with a view to preventing a through current, the first and second transistors M1a and M2a are shifted between the ON and OFF states with a delay with respect to each other.
As described above, in the power supply circuit shown in FIG. 4, the output voltage Voa at the output terminal OUT is divided to produce the feedback voltage Vfba, and the feedback voltage Vfba is compared with the reference voltage Vrefa to detect an overshoot in the output voltage Voa.
In the power supply circuit disclosed in Patent Document 1, the CMOS inverter is controlled so that the output voltage is constant. This achieves fast response to a variation in load. However, no mention is made of a measure against an overshoot in the output voltage.
In the power supply circuit disclosed in Patent Document 2, the pulse width of PWM is controlled to make the output voltage cope with a variation in load. However, no mention is made of a measure against an overshoot in the output voltage.
In the power supply circuit disclosed in Patent Document 3, the direction of the current passing through the smoothing circuit is detected, and the switch is forcibly turned OFF so as to reduce direct-current power loss when the load current is high. However, no mention is made of a measure against an overshoot in the output voltage.
In the power supply circuit shown in FIG. 4, to further reduce an overshoot in the output voltage Voa, it is preferable that the divided feedback voltage Vfba be as close to the reference voltage Vrefa as possible. In that case, however, noise resulting from the switching of the first and second transistors M1a and M2a, or extraneous noise, may cause the feedback voltage Vfba to exceed the reference voltage Vrefa. This inconveniently leads to malfunctioning of the control circuit 10a. 